Many new emerging applications require the use of ultra-low power consumption solutions inside a chip. This will allow them to be incorporated into devices that operate from a small non-chargeable battery for very long periods without the need to frequently charge the battery. For example, wearable, mobile and Medical devices which are battery operated may require an ultra-low power solution.
In parallel the scaling of the silicon manufacturing geometry doubles every 2 years creating larger and faster chips which include many more transistors and logic inside that are running at higher speed and consume more power. In addition to this, the advanced process become less controllable and the difference between the performance of the worst-case device and the best-case device can be more than 5×, so trying to design and ensure that its performance is met for the worst-case condition causes a large overhead during the design and increases area and power dramatically.
In order to enable this increase in speed and size but maintain the power at reasonable levels which can fit battery operated devices there is a need to be able to design the chip for the typical process and temperature and to optimize the operating voltage of the device based on the chip manufacturing corner, temperature and process variations. The optimization of the operating voltage will cause the chip to run with lower voltage than if it was designed for the worst-case conditions and using this method it is possible to reduce the active and leakage power by the square factor of the voltage reduction.
In order that a device which is designed for the typical case will work also at different corners of the process there is a need to measure very accurately the timing of the critical path of the design (critical path is defined as the longest electrical path between two flip-flops of the device, that is to say having the longest transmission) and mimic exactly this path to a First Fail mechanism which can be tested separately from the rest of the device. According to the test results of the First Fail mechanism it is then possible to determine the optimal operating voltage of the entire chip.
Accurate measurement of the critical path inside each device is a complicated task because this path timing can change based on the process corner, temperature and also on the location on the wafer and inside the die. To solve this problem an in-line measurement is needed per chip in order to determine the accurate path delay and to mimic this exact delay inside the First Fail circuit.